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    June 27, 2006

     Anti Hyperthreading or multi news ?
      Posted on 26/06/2006 at 18:30 by Marc
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    Last april 2006, x86-secret said that AMD was looking into an anti HyperThreading outlet for the « K10 ».

    More concretely, this involved having several physics processors as a virtual processor for system use where HyperThreading has a physical processor for several virtual processors in system use. It would be hardware that would dispatch the instructions of the same thread between cores, in trying, for example to guess on parallelism with more or less success where the code doesn’t have a base.

    Since then, things have accelerated. On June 18, Overclockers.ru announced that according to sources close to AMD the functionality would already be in the Athlon 64 X2 AM2 and that it will be activated in the year to come via BIOS, CPU drivers and OS updates. Also publised by our colleagues from The Inquirer last June 23, this information about this AMD's "secret weapon" has already been all aroud the web. Its credibility is low but anything is possible: the edf is in 8th position

    On June 22, someone on the XtremeSystems forum mentioned a new option in the latest bios of the Intel i975x motherboard, « Bad Axe », called Core Multiplexing. They wondered if this was indeed a response to AMD’s secret weapon. After that, there was a 4 pages discussion in which we found amongst other things very nice paint graphics made by Freecableguy that illustrate this possibility and which have been published by many websites. Here again the information was all around the web, graphic included, without sometime indicating their origin (a forum user!). We can't believe it...

    We have to point out that the last information are only rumours and do not deserve all the attention that they have received. The last one, the Core Multiplexing option is normally activated on Intel motherboard and it is indicated that deactivating it... deactivate the second core: how is it possible to believe that it has any type of connection with the technology stated above? Because of its name, we believe that it maybe has something to do with the communication of the two cores with the chipset via the shared FSB.

    If it doesn't parallelise a thread, at least all of this will have multiplied the news…

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