GeForce 9800 GX2: and the partners? DirectX 10.1 is here, first demo Larrabee: Intel remains discreet Intel talks about the Nehalem and post SSE

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GeForce 9800 GX2: and the partners?   Posted on 18/03/2008 at 20:11 by Nicolas

	The release of Nvidia’s new high end « card » has been accompanied by a stampede of announcements from its partners. Amongst these are notably ASUSTeK, Albatron, Point of View, MSI, Foxconn, Zotac, Sparkle, Leadtek, Chaintech, Twintech, XFX and Gainward. Of course, all of these cards are strictly identical except the sticker. In the absence of modifications to the card itself, some offer games in the bundle while the supplementary cost is obviously added to the final cost which is already high (500€). We will just have to wait and see who will offer watercooling as adequate components have been ready for some time now...

DirectX 10.1 is here, first demo   Posted on 18/03/2008 at 19:49 by Nicolas

	The Service Pack 1 for Windows Vista is now available at Windows Update and with it DirectX 10.1 has been introduced. You may recall the new version of Microsoft’s API is supported by ATI Radeon HD 3000s as well as S3’s Chrome 400. Furthermore, a Chinese site has published the PingPong demo used to illustrate ATI’s pdf which presents the advantages of DirectX 10.1 and was discreetly put on-line the day of the GeForce 8800 GT’s release. It is already found with several of our colleagues including NGOHQ.com.

Larrabee: Intel remains discreet   Posted on 18/03/2008 at 19:03 by Nicolas

	In its teleconference, Intel gave little new information on Visual Computing and the Larrabee. Unsurprisingly, the company insists on the flexibility of its platforms (meaning the multi-core CPU, chipset and graphics plus software and associated developer tools) conceived with the above in mind and physics. Moreover, the CPU giant confirmed that the architecture upon which the Larrabee cores are based is similar to that of the Atom and the first demonstrations should be this year. Well aware that the support of developers was crucial if it wanted to break into the 3D market, the firm promises that the software supporting Larrabee architecture will offer unparalleled freedom.

Intel talks about the Nehalem and post SSE   Posted on 18/03/2008 at 08:51 by Marc

	Intel took advantage of a teleconference to inform us on its server and desktop roadmap. The first point is that the Itanium is not dead and in the second half of the year Intel will launch the Tukwila, its 65nm evolution which will be equipped with no less than 2 billion transistors shared between 4 cores and 30 MB of cache. Intel judges that performance gains compared to the previous generation will be more than double but we shouldn’t forget that it is ‘’only’’ a dual core. The Santa Clara giant also made official the Dunnington, the first 6 core processor. Destined for the quad-socket Caneland platform, this CPU derived from Core architecture will be composed of 1.9 billion transistors engraved in 45nm. Furthermore, there will be no less than 16 MB of L3 cache and all of this should see the day in the second half of the year. Of course, the Nehalem was a topic and this after the first official details were given a year ago. It was confirmed that the new architecture which will enter into production in the fourth quarter of 2008 have a shared 3 level cache of 8 MB in addition to 256 KB of L2 and 64 KB of L1 per core. As previously announced, SMT, which allows running 2 threads per core, will also be a component and the integrated memory controller will support 3 DDR3-1333 channels. The Nehalem was announced as being flexible in terms of the number of cores or, in other words, the number can vary from 2 to 8 even if at first it seems Intel will just have 2 and 4 core versions. Intel stresses its advances in terms of IPC (instructions per clock cycle) compared to Core architecture, notably thanks to the management of 128 micro-ops in flight versus 96 for Core. Also, they point out improvements in cache access and branch prediction. New SSE4 instructions will be introduced, specifically destined for word processing (and no, not for Word). While 2009 should feature the arrival of the 32nm version of the Nehalem, the Westmere, the next Sandy Bridge architecture to use the same engraving process is planned for 2010. It will integrate AVX (Advanced Vector Extension), which is no more no less the successor to SSE. Registers will go from 128 to 256 bits and allow working on 3 operands, which is also an idea that will be integrated to SSE5 and already announced by AMD. So, AVX versus SSE5, a big battle in 2010?