For the first time, at the IDF currently taking place in Beijing, Intel has shown off a 32nm wafer of processors using the new “Sandy Bridge” archicture. At the same time, Intel has confirmed that production of this processor will begin in the 4th quarter of 2010, which would mean a launch right at the end of the year or the beginning of 2010.
Although you can’t see much on the wafer, one of the presentation images is more revealing as it shows the die itself. You can see the graphics part (on the left), followed by 4 cores on the right.
You can also see the memory controller and the I/Os on the right. Everything is therefore included on the 32nm die, while the current Core i3/i5s have a separate 45nm die for the graphics and memory, in addition to a 32nm die for the CPU itself. It goes without saying the bandwidth will increase and the latency will decrease, especially as the graphics part will share the processor cache.
Intel has announced moreover an improved IPC and power supply system so as to bring improvements in terms of energy efficiency. To recap, Sandy Bridge will include AVX, which is no more no less than the successor to SSE. AVX increases the current 128-bit wide vector instructions to handle 256-bit wide instructions and will enable the processing of 3 operands, an idea that will also be integrated in AMDs SSE5 and which will help with CPU/GPU fusion.