Intel has just made the official presentation of its 22nm engraving technology which should result in the release of products towards end 2011 / beginning 2012. The big surprise is the inclusion of Tri-Gate technology that wasn’t expected for this generation but rather for the next. Intel (and other industry players) have carried out multiple demonstrations of Tri-Gate over the last few years and Intel will be the first to launch a manufacturing process using the technology for all transistors. Ivy Bridge processors are set to be Intel’s first 22nm CPUs.
The concept behind Tri-Gate is relatively simple. Instead of making transistors on a plane (planar = 2-D), a third dimension has been added in the form of a small sprocket in the channel
, which is where the name FinFET, used by other manufacturers for Tri-Gate, comes from). Without having any impact on density, this addition increases the contact area of the gate on the substrate (in yellow/blue), now on three planes, which is where the name Tri-Gate comes from.
By increasing the contact area the technology has the advantage of reducing current leakage when the transistor is off. Another advantage of this new geometry is that you can increase the number of fins very easily to create higher performance transistors. This is what you can see on the illustration above, with a Tri-Gate transistor using just one fin on the left and another with three fins on the right that will increase transistor performance, to the detriment of density of course.
On the first blue curve on the right, Intel is showing the gains you can obtain in current leakage at the same voltage (lower energy consumption at idle). The second blue curve, on the left, shows another calibration of the process where you can choose to reduce the voltage at which the transistor is switched on. In this case the energy consumption in load is lower. In practice there’s a possible performance increase of 37% at low voltage (18% at higher voltage), or rather up to a 0.2V gain in power reduction of the transistor, at constant performance. For comparison, when the 32nm engraving process replaced the 45nm process there was a performance increase of between 14 and 22%.
Intel hasn’t really said which solution it will go for on its future products but we imagine that they will have two distinct nodes, as they do for 32nm: one for desktop/mobile processors (the P 1270) and another for ultramobile applications (SoC, the P1271). Energy consumption at idle has up to now been one of the main breaks on Atom architecture being used on ultra mobile applications (we’re still waiting for the first x86 smartphones, which were, remember, re-announced by Intel at this year’s CES), so the gains here are good news for the SoC version.
At a time when Intel hasn’t yet broken into the smartphone and tablet markets and ARM competition is extending into other segments (2012), Intel, with this announcment, is reminding the rest of the industry of its technological domination in terms of photolithography fabrication processes. The 22nm Tri-Gate process is a serious weapon that Intel will no doubt use to good effect, but unless there’s a drastic change in strategy on Atom, don’t expect to see 22nm coming rapidly on these platforms as Atom Nettops/Netbooks and SOCs (D/N/Z ranges) are still engraved at 45nm. The launch of 32nm Atoms (Cedar Trail
) are only slated for the end of the year, which is two years after the launch of the 32nm process.