Home  |  News  |  Reviews  | About Search :  HardWare.fr 



ProcessorsMotherboardsGraphics CardsMiscellaneousHard DisksSSD
Advertise on BeHardware.com

News of the day

  • Future AMD architecture : 128 KB of L1
  • Updated survey : 13 LCD 20 inches 5, 6, 8, 16 ms
  • LCD LED, OLED, SED : some delays
  • AMD Torrenza, co-proc for Opteron
  • AMD Direct Connect 2
  • Archives

    Juin 2006
    LMMJVSD
    1 2 3 4
    5 6 7 8 9 10 11
    12 13 14 15 16 17 18
    19 20 21 22 23 24 25
    26 27 28 29 30

    You can read previous news using our archives.

    << Previous day's news
    June 1er, 2006
    Next day of news >>
    June 5, 2006



     Future AMD architecture : 128 KB of L1
      Posted on 02/06/2006 at 19:51 by Marc
    Imprimer cette news Envoyer cette news par e-mail

    Update :A chief engineer of AMD said to Real Word Tech that the cache L1 for data and instructions would be of 64 KB each and 128 KB total. This is the same size as the K8 which is rather good news since it will be combined with lower latency and double bandwidth (2x16 bytes / cycle, as compared to 2x8 previously). We would however appreciate that AMD indicates L1D when it communicates the size of this cache instead of writing L1, which in fact correspond to the sum of L1D + L1I…

    During AMD Technology Analyst Day, AMD unveiled some information about the cache size of the new architecture. This architecture is sometime named K8L but this code name hasn’t been confirmed by AMD.

    We already know the L2 cache size, 512 KB per core and the L3, 2048 KB shared. We know now the cache L1 which will be of 64 KB per core : this is similar to the Pentium M / Core Duo / Core 2 Duo architecture, but it is two times less than a K8.

    AMD would have indicated that this modification was logical because of the addition of the cache L3. This explanation hasn’t really convinced us because of the performance gap between these two types of cache. Also, working with 64 bits for example increase the pressure on the cache.

    The cache L1 latency will however be reduced in compensation and AMD announced a doubled transfer rate (32 bytes / cycle). Of course, there were probably some restrictions because of the die dimension and some elements’ size had to be reduced. We would however have preferred that these improvements were made without size reduction even if we imagine that the reduction due to this modification will be largely compensated by the other improvements of this architecture.



     Updated survey : 13 LCD 20 inches 5, 6, 8, 16 ms
      Posted on 02/06/2006 at 17:52 by Vincent
    Imprimer cette news Envoyer cette news par e-mail

    5 new monitors join the 20’’ monitor survey published last month. They all deserve a good look:


  • Asus PW201 : MVA 8 ms panel, zero bright dead pixel warranty (ZBD)
  • Dell 2007WFP : just released, we know that this monitor will be one of the best sellers in the world.
  • Fujitsu-Siemens S20-1W : P-MVA 8 ms panel in an impressive metal bezel.
  • LG Flatron L2000P : the first IPS 8 ms.
  • Samsung SyncMaster 215TW : 21 inches for the price of 20.

    > Updated survey : 13 LCD 20 inches 5, 6, 8, 16 ms



  •  LCD LED, OLED, SED : some delays
      Posted on 02/06/2006 at 15:35 by Vincent
    Imprimer cette news Envoyer cette news par e-mail

    Bad news, new technologies of monitor will all be delayed. LED backlight monitor awaited for this summer will only be released in October. OLED monitors to be released in October will be postponed until a future unknown date.

    Finally, and we already knew that, Canon and Toshiba SED panels (only reserved to TVs) won’t be release end of 2006 or early 2007. The manufacturers think now that they will release them just before the Olympic Games in China that will take place in August 2008.



     AMD Torrenza, co-proc for Opteron
      Posted on 02/06/2006 at 14:38 by Marc
    Imprimer cette news Envoyer cette news par e-mail

    AMD announced the introduction soon of the Torrenza technology for Opterons. This code name corresponds to an open architecture which will include additional co-processors directly via the HyperTransport. The objective is to reduce latencies as central memory and Opteron accesses will be direct and will no longer be made thought different intermediate such as the chipset if they are on a bus such as the PCI Express.


    Initially, the integration will be with a module that will fit in an Opteron Socket. This concept isn’t new, the DRC company already announced end of April a module based on Xilinx Virtex 4 programmable co-processors. This module fits in a Socket 940 and can directly access an adjacent Opteron and RAM memory.

    AMD’s willingness to generalise this HyperTransport aperture to co-processors would however provide new attractive possibilities for specialised sectors while waiting for the integration of co-processors in the same packaging or even in the same die in the years to come.



     AMD Direct Connect 2
      Posted on 02/06/2006 at 14:18 by Marc - source: DailyTech
    Imprimer cette news Envoyer cette news par e-mail

    AMD already announced in public roadmaps the release in 2008 of the Direct Connect 2 architecture. Without giving more information about the date, the manufacturer has communicated more specific details. If each Opteron currently has 3 HyperTransport 16 bits links, this number will be increased to 4. It will also be possible to split each link into two 8 bits links.


    With this possibility, it will be possible for example to have computers with 8 new generation Opteron or 32 cores. Each core will be directly connected to the 7 other and to a chipset via the last remaining HT bus. The design of these motherboards will surely be impressive!


    << Previous day's news
    June 1er, 2006
    Next day of news >>
    June 5, 2006


    Copyright © 1997- Hardware.fr SARL. All rights reserved.
    Read our privacy guidelines.