Written by Marc Prieur
Published on March 18, 2008

URL: http://www.behardware.com/news/lire/18-03-2008/#9498

Intel took advantage of a teleconference to inform us on its server and desktop roadmap. The first point is that the Itanium is not dead and in the second half of the year Intel will launch the Tukwila, its 65nm evolution which will be equipped with no less than 2 billion transistors shared between 4 cores and 30 MB of cache. Intel judges that performance gains compared to the previous generation will be more than double but we shouldn’t forget that it is ‘’only’’ a dual core.

The Santa Clara giant also made official the Dunnington, the first 6 core processor. Destined for the quad-socket Caneland platform, this CPU derived from Core architecture will be composed of 1.9 billion transistors engraved in 45nm. Furthermore, there will be no less than 16 MB of L3 cache and all of this should see the day in the second half of the year.

Of course, the Nehalem was a topic and this after the first official details were given a year ago. It was confirmed that the new architecture which will enter into production in the fourth quarter of 2008 have a shared 3 level cache of 8 MB in addition to 256 KB of L2 and 64 KB of L1 per core. As previously announced, SMT, which allows running 2 threads per core, will also be a component and the integrated memory controller will support 3 DDR3-1333 channels.


The Nehalem was announced as being flexible in terms of the number of cores or, in other words, the number can vary from 2 to 8 even if at first it seems Intel will just have 2 and 4 core versions. Intel stresses its advances in terms of IPC (instructions per clock cycle) compared to Core architecture, notably thanks to the management of 128 micro-ops in flight versus 96 for Core. Also, they point out improvements in cache access and branch prediction. New SSE4 instructions will be introduced, specifically destined for word processing (and no, not for Word).


While 2009 should feature the arrival of the 32nm version of the Nehalem, the Westmere, the next Sandy Bridge architecture to use the same engraving process is planned for 2010. It will integrate AVX (Advanced Vector Extension), which is no more no less the successor to SSE. Registers will go from 128 to 256 bits and allow working on 3 operands, which is also an idea that will be integrated to SSE5 and already announced by AMD. So, AVX versus SSE5, a big battle in 2010?