Dailytech has published some new information on the next G3x socket which will be used by AMD for certain massively multi-core processors. You may recall, they were already mentioned by this company during the presentation of the Montreal processor and G3MX technology (Socket G3 Memory Extender).
According to our colleagues, the G34 socket will accompany the second generation of 45nm processors (the first usually used the AM2+ or AM3 if DDR3 was desired) starting in 2010. The Sao Paolo, an octo-core CPU, described as a double native "Shanghai" quad core, should be the first to adopt it and a 12 core known as the Magny-Cours should follow. Both will use the four HyperTransport 3.0 lanes, have 12 MB of L3 cache and 512 KB of L2 cache per core. In addition, the G34 should enable their embedded memory controller to support DDR3 on 4 channels.
One interesting detail is that the 3 HT lanes being enough for a motherboard which can house 4 CPUs, the fourth could be used for
Torrenza, an architecture that enables adding co-processors.
