Stepping E0 for the Core 2 Q9550 Posted on 30/05/2008 at 16:50 by Nicolas
- source: Intel PCN
After the Xeon "Harpertown" and "Wolfdale-DP", E3110 as well as the Core 2 Duo E8400 and E8500, it’s now the Core 2 Quad Q9550 and Xeon "Yorkfield" X3350 and 3360 which will adopt stepping E0.
The S-Spec goes from SLAWQ to SLB8V for the Q9550, from SLAX2 to SLB8Y for the X3350, and from SLAWZ to SLB8X for the X3360. As they previously used the C1 revision of the Penryn core, the CPUID changes from 0x10677 to 0x1067A. Other modifications are classic: the Power Status Indicator (PSI) is now supported (if the motherboard allows it) and there is ACNT2, which enables the P-state (Performance state) to be more efficient.
There were also modifications to the PECI (Platform Environmental Control Interface), XSAVE/XRSTOR instructions were added, and the CPU package no longer contains halides. Note that the Xeon X3320 is also concerned, but it goes from stepping M1 to R0 as it only has 6 MB of L2 cache versus 12 MB for the two other models. Its S-Spec goes from SLAWF to SLB69.
After the Xeon "Harpertown" and "Wolfdale-DP", E3110 as well as the Core 2 Duo E8400 and E8500, it’s now the Core 2 Quad Q9550 and Xeon "Yorkfield" X3350 and 3360 which will adopt stepping E0.