Stepping E0 for the Core 2 Duo adds some changes Posted on 23/05/2008 at 14:25 by Nicolas
- source: Intel PCN
While the transition from stepping C0 to stepping E0 meant practically no changes for the "Harpertown" and "Wolfdale-DP" Xeons (except for the X5482 whose TDP went from 150W to 120W), things seem to be noticeably different for the Core 2 Duo E8400 and E8500 as well as with the Xeon E3110.
Besides the S-Spec which changes from S LAPG to SLB9J for the E8400, from S LAPK to SLB9K for the E8500, and from SLAPM to SLB9C for the E3110, the CPUID evolves from 0x10676 to 0x1067A. However, now there is especially Power Status Indicator (PSI) support (if the motherboard approves) and ACNT2 has been added which enables the P-state (Performance state) to be more efficient.
Changes were added to the PECI (Platform Environmental Control Interface), there are now XSAVE/XRSTOR instructions (a new ISA extension to save/restore the "context" of x87, SSE amongst others), and finally the CPU package no longer contains halides.
A bios update for the motherboard will of course be necessary to make these CPUs function. Otherwise, it will be interesting to see in practice whether a very recent motherboard which supports all of these options will show significant improvements in power consumption and overclocking.
While the transition from stepping C0 to stepping E0 meant practically no changes for the "Harpertown" and "Wolfdale-DP" Xeons (except for the X5482 whose TDP went from 150W to 120W), things seem to be noticeably different for the Core 2 Duo E8400 and E8500 as well as with the Xeon E3110.