AMD is taking advantage of the CeBIT to show journalists that the Shanghai and Deneb, the server and desktop versions of its next 45 nm quad core CPUs, are functional.
These were produced in the Dresden Fab 36 on 300mm wafers. The manufacturer also used the event to stress the "performance per watt" ratio of its future processors and not simply performances, a sign that in the short term they will not be able to rival Intel on the very high end.
Expected out in the second half of 2008, these CPUs will have an L2 cache of 512 KB per core, a shared L3 cache which can be as high as 6 MB and they will still fit into the Socket AM2+ and support DDR2. We will have to wait until 2009 to see AM3 versions which will support DDR3.
