AMD: SSE5 the Bulldozer

AMD has revealed a new set of instructions, baptized SSE5, which extends those of the good ole’ x86 (!). Composed of 46 base instructions it will be integrated in the future «Bulldozer» core expected out in 2009 which is based on an entirely new architecture. The «Bulldozer » will be integrated to various solutions ranging from the octo core « Sandtiger » to the « Falcon », a quad core CPU stemming from the Fusion project and which will also have an integrated GPU.

By immediately unveiling in detail the functioning of this new technology via a 254 page PDF document , its creator thus intends to allow developers to anticipate its release and therefore facilitate its introduction. SSE5 notably differs from its predecessors with the new ability to work on 3 or even 4 operands consolidated into a single instruction. This was previously limited to 2.

Following the example of all instruction sets that have been released since MMX, SSE5’s goal is to increase performances by accelerating the processing of data. However, AMD still is vague about the type of applications that will benefit the most and only hastily mentions high performance computing, multimedia and security.

As for the name, while it is clever to use the three letters which we readily attribute to Intel, the origin of the previous four versions, this could cause some confusion. Indeed, the Barcelona only partially supports SSE4 and nothing indicates that its successors will go even further. In the opposite direction, could Intel adopt the use of SSE5? And if not, will Intel directly move to « SSE6 » ?

You may recall that in 1998 AMD already introduced a SIMD instruction set, 3DNow!, implemented in the K6-2. Contrary to Intel’s MMX which was limited to integers and shared its registers, it allowed working with real numbers. Despite good results in certain optimized applications, Intel never really integrated 3DNow! and preferred to work on its own SSE.