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     IDF : Intel to annonces SSE4
      Posted on 27/09/2006 at 20:12 by Damien
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    Pat Gelsinger, Senior Vice President and General Manager of Digital Enterprise group, unveiled a new set of instructions during the second keynote: the SSE4. This new instruction set is announced as the most important evolution since the SSE2 and will be introduced with the first 45 nm CPUs of the manufacturer. These processors will be codenamed Penryn, will be introduced in 2007 and based on the Core 2 Duo architecture.


    This new instruction set will improve multimedia performances, research and detection algorithms and data protection (CRC etc.). It will also facilitate the vectorization. Vectorizing the code is often something that is very difficult to do for developers and Intel perfectly understood that facilitating this operation would be the best way to increase performances. It is also interesting to note the release of DPPS and DPPD (Dynamic Power-Performance Scaling and double precision) instructions described by Intel as intended to support languages such as HLSL…

    Intel published today the list and description of new instructions but full details of their use will only be available once everything will have been tested with the first functional 45 nm chips (this will probably happen soon).


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