AMD announced the introduction soon of the Torrenza technology for Opterons. This code name corresponds to an open architecture which will include additional co-processors directly via the HyperTransport. The objective is to reduce latencies as central memory and Opteron accesses will be direct and will no longer be made thought different intermediate such as the chipset if they are on a bus such as the PCI Express.
Initially, the integration will be with a module that will fit in an Opteron Socket. This concept isn’t new, the DRC company already announced end of April a module based on Xilinx Virtex 4 programmable co-processors. This module fits in a Socket 940 and can directly access an adjacent Opteron and RAM memory.
AMD’s willingness to generalise this HyperTransport aperture to co-processors would however provide new attractive possibilities for specialised sectors while waiting for the integration of co-processors in the same packaging or even in the same die in the years to come.
