IBM, GlobalFoundries and Samsung held their Technology Forum last week. The three companies have been working together on the development of fabrication processes. Without making any detailed announcements, the various sessions have given us a view on a few interesting points.
First of all, there will be no partially depleted SOI (PD-SOI) with the 28nm fabrication process developed by GlobalFoundries and its other partners. PD-SOI is difficult to implement effectively at lower engravings, which limits the interest of the technology. While PD-SOI has indeed been put on the discard pile (it has been confirmed that it will not reappear with 20nm), this doesn’t mean that we have seen the last of SOI. According to Dr Gary Patton from IBM, as of 20nm and onwards we’ll be seeing ETSOI. ETSOI (extremely thin SOI) is planar fully depleted SOI, designed to counter the effects of standard SOI. While IBM brought up ETSOI several times, its partners, who aren’t working on this area, didn’t mention it. The extended development time and increase in direct costs of wafers may well push the different Common Platform players to offer, for example, one process with ETSOI and one without to satisfy customer demands. IBM confirmed in passing that ETSOI has been developed for the 20nm process in collaboration with ST Micro.
There was an announcement with respect to the 20nm process and the necessity of double patterning. The technology consists in using two successive exposures with different masks to achieve a single metallic layer. Although not all layers require double-patterning, the addition of masks makes for considerable additional costs. The slide below gives a breakdown of the impact on costs moving from the 32/28 nm to the 22/20 nm processes:
The additional mask costs are particularly high as are those for design tools (EDA) and the design itself, which rockets due to the complexity of double patterning. Intel is also likely to call on such techniques for the 16nm process, though not for 22nm as far as we know.
Another definite, though pretty much expected, announcement was the arrival of FinFET transistors. Remember, Intel decided to modify the form of transistors as of 22nm (which will soon be arriving with the launch of Ivy Bridge), introducing 3-D instead of the previously planar construction (see this news on the subject
for more details). The members of the Common Platform have confirmed that it should be introduced for the 16nm process, something that had previously been assumed.
Doubling the density of each node is accompanied by performance gains announced as being 1.6x
For the horizon beyond 10nm, which is considered to be a technological barrier for current methods, IBM talked about several possible solutions including using carbon nanotubes. IBM announced that it has developed new methods for sorting those nanotubes that are useable from those that aren’t more effectively. Gary Patton said that 30% of semiconductor nanotubes produced act as a a plain conductor and therefore should be deleted. With respect to EUV lithography, which we’ve been waiting for for several generations, we’ll have to wait a little longer. While IBM did leave the door open for 16nm, it's more probable that the technology won’t be ready by then.
During the conference we noted several other points. On several occasions there were allusions to the fact that the Common Platform 28nm fabs were running and hadn’t been halted. This was a reference to a relatively surprising article published by SemiAccurate
last week, which claimed that TSMC had “halted 100% of 28nm production in mid-February” for an undisclosed reason. This information is difficult to verify and while we were at one point aware of rumours concerning delays in the delivery of certain GPUs produced by TSMC, the rumours have since stopped. Multiple references to this rumour by TSMC’s competitors was opportunistic to say the least.
Finally we learnt from Subramani Kengeri from GlobalFoundries that while CPU and GPU production have up until now been the driving forces behind the development of technology processes, today it’s SoCs and low energy consumption chips that are forcing design decisions. AMD will be happy.