Samsung are the first to announce the production of an 8 GB flash memory using the toggle DDR 2.0 interface. This interface gives an impressive 400 Mbps transfer rate compared to 133 Mbps for the toggle DDR 1.0 introduced by Samsung in 2009 and also supported by Toshiba, and 40 Mbps for standard flash.
For comparison, the competitor ONFI 2.x interface supported by Hynix and IMFT gave 200 Mbps and the next 3.0 version also has a transfer rate of 400 Mbps. The two interfaces should eventually be compatible, with both groups working on their standardisation within JEDEC.
With a sinlge chip interfaced with an 8 bit bus it will be possible to manage 400 MB/s as long as the memory itself can keep pace, which is unlikely to be the case at first. This will open the door to high performance flash memory storage device designs which don’t require an increasing number of channels, unlike SSDs, as long as the chip capacity is sufficient of course. Samsung says that its chip is engraved at a “20nm class” process but hasn’t detailed the fineness of the engraving exactly (20? 25? 29?).
