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- AFDS: AMD unveils FSA for OpenCL
- AFDS: The future AMD GPU architecture!
- AFDS: Is OpenCL gaining ground?
- AFDS: AMD Fusion 11 Developer Summit
- Report: AMD Radeon HD 6790
- Crysis 2 DX11, performances & tessellation
- Nvidia GeForce GTX 560 & Asus DirectCU II TOP
- Optical LightPeak on the Sony VAIO Z!
- AFDS: Microsoft announces C++ AMP
- AFDS: Back to the future of AMD GPUs
- Radeon HD 7000M, GeForce 600M: renaming
- High-end GeForce GTX 580 roundup
- GTX 580 3GB vs 1.5GB, SLI, surround
- The impact of PCI Express on GPUs
- H.264 encoding - CPU vs GPU



 Crysis 2 DX11, performances & tessellation
  Posted on 03/08/2011 at 14:19 by Damien
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Following the release of the DX11 pack for Crysis 2, we decided to revisit the performance of various graphics cards in this game, an opportunity to detail its up-to-date effects and observe the use of tessellation in detail.

> Crysis 2 DX11, a closer look at performance and tessellation



 Nvidia GeForce GTX 560 & Asus DirectCU II TOP
  Posted on 22/07/2011 at 14:20 by Damien
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After the GeForce GTX 560 Ti, NVIDIA is back with a model without the 'Ti' suffix. To get a better handle on this GTX 560, we put the Asus DirectCU II TOP through its paces...

> Nvidia GeForce GTX 560 & Asus DirectCU II TOP



 Optical LightPeak on the Sony VAIO Z!
  Posted on 28/06/2011 at 15:32 by Marc
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Sony has just announced a new VAIO Z. Weighing a little under 1.18 Kg and measuring 16.65mm thick, it has a choice of CPUs from the Core i5-2410M to the Core i7-2620M, 4 to 8 GB of DDR3-1333, 128 to 512 GB of SSD and either a 1600 x 900 or 1920 x 1080 pixel panel for between #1454 and #3634 (all the trimmings!).


What we’re really interested in however is what Sony is calling the Power Media Dock. This additional external part weighs 685g and costs #400. It integrates a DVD rewriter (or #525 for the Blu-ray writer version) and a network Gigabit port as well as a USB 2.0 port and USB 3.0 ports.


Better still, there’s a Radeon 6650M chipset with 1 GB of GDDR3 inside which gives better performance than the Intel HD Graphics 3000 used in the Core i7 and allows you to run up to 4 screens (2 via the IGP, laptop screen included, and two via the HDMI and D-Sub outs on the Power Media Dock).


To connect the Power Media Dock you have to use the laptop USB 3 connector. While it is compatible with USB 3 peripherals, it also uses LightPeak technology (optical) as you can see in the photos of the inside of the laptop, which is a first! There’s a strong resemblance to the first demos of LightPeak which also used a modified USB port, as was the case at IDF 2009.


This implementation is therefore different to that of Thunderbolt launched jointly by Intel and Apple in February, which uses a DisplayPort connector rather than a USB 3.0 and is copper and not optical (MacBook Pro 2011). This Thunderbolt connector can give a transfer speed of 20 Gbps, the bandwidth being separated equally between two channels, one designed for the DisplayPort and the other PCI-Express. Sony may well have implemented this specific use of LightPeak to push data bandwidth without cutting down graphics performance too much, with Intel LightPeak being connected to the rest of the PCI-Express x4 system at 16 Gbps.


This looks like a good solution for connecting up an additional graphics card but being proprietary, it lacks flexibility. No way of upgrading this graphics part then, though AMD was already looking at an open solution back in 2008 with the External Graphics Platform (XGP). Since then things haven’t moved forward and laptop manufacturers would obviously rather sell a new machine than allow an upgrade of older ones. It remains to be seen if the forthcoming PCI-Express x4 (32 Gbps) external cables on which PCI-SIG is working will have the same fate.



 AFDS: Microsoft announces C++ AMP
  Posted on 17/06/2011 at 00:35 by Damien
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Microsoft chose to present a new version of C++ at AFDS. It is optimised for GPUs and, potentially, all types of accelerator. Called AMP (Accelerated Massive Parallelism), this extension supplements C++0x and Parallel Patterns Library (PPL) to facilitate the writing of code which will include functions designed to be accelerated by the GPU.


Herb Sutter, Software Architect at Microsoft and C++ guru, insisted on the importance of not making the language too complex and making do with additions that were as simple as possible by making the most of what is implicit in C++ and allowing the compiler to take care of the burden linked to the use of such accelerators.

Thus, only two innovations come in at language level. The first, array_view, enables the representation of a non-uniform, incoherent and/or disjoint memory without having to specify .copy()/.sync()s explicitly. This level of abstraction will simplify the code a good deal.

The second is called restrict(). As it’s name indicates, it allows to specify restrictions linked to a certain architecture for certain functions. These concern limitations inherent in current accelerators and indicate implicitly that a piece of code has significant parallelism and can be executed on a GPU for example. Microsoft’s first version of AMP C++ builds on the in-house DirectCompute 11 API using only restrict(direct3d), restrict(cpu) being the implicit default mode. Microsoft is thinking about a restrict(pure) in the future which would have no restrictions but would declare parallelism to the compiler.


Standard code on the left, AMP C++ on the right.

No other language component will be introduced, with all the rest being implicit. For example, attaching “const” will be interpreted as “read only”. Microsoft says here however that there is currently no similar way of specifying that elements are “write only”, which could be useful in the future.


A demonstration made by Microsoft highlighted the possibility, with a single executable, of putting any type of hardware to use: CPU, GPU, APU, APU + GPU, double GPU…

All this should come with the next version of Visual Studio. Microsoft moreover intends to make AMP C++ an open standard so that it can be exploited on different platforms, whether this be at the compute interface or operating system level. Herb Sutter announced that they were working directly with AMD so that AMD could offer an FSA version. ARM also seems interested in this development. NVIDIA seems to have been surprised by this announcement and reacted on its blog by saying that it welcomed any development that facilitates the harnessing of GPU processing power, that the initial AMP version was for DirectCompute 11 and that its GPUs would also benefit. Nothing on a CUDA version of AMP however…



 AFDS: Back to the future of AMD GPUs
  Posted on 16/06/2011 at 20:34 by Damien
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At the last keynote at AFDS, Eric Demers, Chief Technology Officer for GPUs at AMD, went back over the future GPU architecture that was presented in great detail this week, highlighting the main areas more simply. It was also confirmed that AMD hoped to launch this architecture at the end of the year, if the 28nm fabrication process doesn’t hold things up.

Eric Demers reminded us that ATI/AMD GPUs had gone from a vec4+1 architecture to a vec5 as of the Radeon HD 2900s, then towards a vec4 architecture with the Radeon HD 6900s, which will be used in the forthcoming mid range GPUs as well as in Trinity. These architecture choices can be explained by the fact that graphics rendering, still the main usage for GPUs, implies numerous vec4 and scalar operations. The flexibility of MIMD/VLIW type processing units in the latest GPUs has allowed AMD to dispense with the scalar channel and let the compiler handle the mixing of all operations in the 5 or 4 available channels.

With its future architecture, AMD wanted to keep a similar set-up. While the VLIW model has been abandoned, the fundamental blocks of these GPUs will still have these four channels, not to carry out vec4 operations but to keep a similar ratio seen as the best adapted for graphics. With "compute” style tasks, which often make less use of vec5 or vec4 units, becoming more and more important, it was necessary to return to a scalar model from the point of view of the programmer.




The new AMD architecture allows the combination of these two aspects by placing, not one big MIMD unit in each Compute Unit, but rather four small independent SIMD units. AMD adds a scalar unit to them which will be designed to stop vector processing power being monopilsed by simple operations. As with the fundamental blocks on current GPUs, each CU will have four texturing units. In terms of execution units, a CU is therefore very close to what AMD currently calls the SIMDs. It’s how these execution units are used which represents the radical change. The Cayman GPUs used in the Radeon HD 6900s can indeed be seen as an intermediary step in this new architecture. This hybrid/prototype nature might go some way to explaining their debatable effectiveness.

Another important aspect of the new architecture is multitasking as these new GPUs will be capable of processing different commands simultaneously as well as deciding what priority to give to each of them. All this will take place at GPU level and not at operating system level.

The third major development is the L2 cache that can be used in reads and writes. It also enables the existence of a coherent space between all the CUs and the CPU, whether within an APU or with a discreet graphics card.

This generalised L2 cache, the scalar functioning of processing units, support for the x86 virtual memory space and C++ will bring about a huge increase in interest in GPU computing. Note however that on some of these points, AMD is simply making up ground lost to NVIDIA.



One important question we have with respect to this new architecture is how energy efficient it is. As we saw with the Radeon HD 6970s, energy efficiency was slightly down. Increasing the yield of a Compute Unit will therefore increase its relative energy consumption. While the 28nm engraving process does enable a lowering of absolute energy consumption, this remains an important question.

We were able to ask Eric Demers about this and according to him it isn’t too much of a problem. In the current architecture, when some vec4 or vec5 unit lanes aren’t used, they still draw power. They don’t draw as much as when they’re in use, but they nevertheless waste a lot of energy. This won’t be the case in the future architecture. In other words, we will probably get closer to the maximum energy consumption of the Compute Units, but their energy yield is likely to be improved.

Finally we asked AMD’s CTO if, in the future, he was planning to include more CUs in GPUs than is allowed by the TDP, in view of the fact that they wouldn’t all be used in 3D rendering (limited by PowerTune for example) but could be in the compute mode which doesn't use much certain power hungry parts of the GPU (eg. texturing units). Eric Demers replied that AMD was thinking about this and that such an option could perhaps be explored in the future if justified in simulations, notably for a SKU designed for HPC.


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