Home  |  News  |  Reviews  | About Search :  HardWare.fr 

MiscellaneousStorageGraphics CardsMotherboardsProcessors
Advertise on BeHardware.com
Review index:
IDF: Interview with Intel's Mark Bohr
by Guillaume Louel
Published on September 18, 2012

As part of our coverage of the 2012 Intel Developer Forum, we had the opportunity to sit down for an interview with Mark Bohr. Holding both the title of Senior Fellow and Director of the Process Architecture and Integration at Intel, Mr. Bohr - who joined Intel in 1978 - is responsible for evaluating the different technologies that end up in the lithography processes used by the company. One of his current tasks is, as he described himself earlier in the morning leading to our interview, selecting the technologies that will end up being used in Intel's upcoming 10 nm process (expected around 2015 in production). We had the opportunity to cover a large range of topic from the ASML investment to the currently in use processes and upcoming research. In order to ease comprehension, you will find below that we've added some extra references between square brackets. This interview is also available translated in French.

HFR : Last July, ASML announced a co-investment program targeted at its customers, Intel being one of them. Intel was the first company to take on the offer with a $4.1 billion investment. On Monday we've learned that the ASML board approved the deal. You must be satisfied about it?

Mark Bohr : Well, I think it's clear that from Intel's perspective, having EUV [Extreme Ultra Violet lithography] technology and having 450mm EUV tools is very critical to our future, so that's why we made this investment. So am I happy? Yes! It will really help to further ensure that we will have that technology when the time comes.

As we see cost and complexity of processes ever increasing from node to node, do you think that we're going to see in the future a trend where we see a tighter coupling between foundries and their tool manufacturing suppliers?

MB : I think EUV technology is a unique case, it's a very critical technology and a very difficult engineering task and a very expensive technology to develop, so that's why there has to be, in this one case, more collaboration or support between customers like Intel and ASML.

Since you're talking about EUV, there seems to still be a lot of issues right now. This morning during a press briefing you mentioned the wafer throughput [the number of wafer per hour processed, 50-100 per hour being mentioned by Mark Bohr as a minimum in order to seriously consider adopting EUV] was still very low. Another one seems to be that EUV seems to have a slightly hard time scaling down, at least when it comes to ASML delivering their R&D tools?

MB : I think it's premature to conclude that, after all, today we are printing and manufacturing 22nm dimensions using 193nm light, and EUV is a big step downward from that. If you're asking if it's more difficult for EUV to pattern 16nm dimensions vs 22, yes, but I think its well within the capabilities of EUV. Patterning small feature sizes is less of a challenge than getting the throughput up, and a high intensity light source.

Another issue often mentioned with EUV is mask defects, did you see any improvement on that end recently?

MB : I think the industry is making steady progress on reducing mask defects, so I don't think, in my view, that's not one of the top showstoppers but it's one of the two or three challenges with EUV. And of course, although those EUV masks are pretty complex, even today's 193nm phase shifted immersion masks are very complex things that looked very frightening, you know, 10 years ago, but today are pretty commonplace in being made and used.

And today you have very low defect on those.

MB : And very low, right.

The other part of the investment is regarding 450mm wafers, although reading the agreement it seemed that it was specific to EUV 450 mm tooling, correct?

MB : Yes.

Intel has been pushing for 450mm for a long time, a longer time than your competitors. Do you see any progress there?

MB : I haven't been involved with the latest discussions with our vendors but I sense there's a growing consensus. Two new fabs that Intel is constructing, D1X in Oregon and Fab 42 in Arizona, both of them are more than halfway through construction. There are both initially being fitted with 300mm tools but they are designed and intended to eventually be converted to 450mm tools. But not for the first node, not for 14nm. Maybe 10 or 7nm.

Last year we saw an announcement of the Global 450 consortium - of which Intel is a part of - regarding the industry wide adoption of 450mm tools with a significant investment in New York, is there any update on that?

MB : No, I don't have an update on that.

More generally, what is your take on this kind of opportunity with ASML, being able to guide the direction of their research?

MB : We always depend on vendors to develop the tools, sometimes all we need to do is simply collaborate with them, share with them what our needs and targets are, and they'll develop the right tools. But in the case of EUV, the engineering challenges are pretty significant and they required more involvement to the point of an actual investment to make that happen.

This morning you talked a bit about TriGate and that you learned many things from the high volume manufacturing of Ivy Bridge and that it gave you some lessons for the HVM of Haswell, can you give us some insights on changes from process or design that would be pushed on the production of Haswell?

MB : What I tried to say is that Ivy Bridge is Intel's first product on 22nm TriGate, and at the beginning of any new technology generation, you're still debugging yields and performance, but that now has been debugged. So Ivy Bridge was the test case for debugging the process and now all future products will benefit from that, whether they are Haswell or our SoC products, they will all benefit from the yield learning and manufacturing learning that happened on Ivy Bridge.

Did you learn things from the way the transistors and the process behave that maybe you wouldn't have seen during the ramp-up phases?

MB : Well, the learning was mostly related to how do you get the lowest defects and the highest possible yields. So it's a matter of fine tuning the equipment in the fab to eliminate defects and to get dimensions tightly controlled that didn't necessarily impact Ivy Bridge performance and power. That's maybe a separate design tweak that we've done. But in terms of manufacturing yields, that was done on Ivy Bridge and all the subsequent products will benefit from that.

As much as we'd love to measure the performance of the transistors, we can only look at the complete products and try to infer the role of the transistors behind them. When comparing somewhat similar mobile or desktop SKUs from the Sandy Bridge (32nm) and Ivy Bridge (22nm) generation we saw a pretty significant reduction when it comes to power consumption in load, but pretty similar power consumption on idle. Would it be accurate to take from that that in 22nm TriGate transistors as implemented in Ivy Bridge, you favored lower load power consumption by reducing the threshold voltage of the transistors instead of optimizing more against sub-threshold leakage?

MB : It's a little more complicated than that. Ivy Bridge is a tick, no major architectural changes, just compacted to the new process. But the graphics that's part of Ivy Bridge was a major redesign compared to Sandy Bridge and I think we roughly doubled the number of graphics transistors, so you got many more transistors burning some leakage power. If you look at the total chip leakage, you have to keep in mind that graphics was significantly expanded. And the Ivy Bridge product is intended for different markets going from higher performance versions to lower leakage but we can do, are doing and will do both lower leakage and higher performance versions.

And with the P1271 process (the SoC version of Intel's 22nm process) you're focusing more on lower leakage, correct?

MB : Yes, from both a process perspective and a design perspective.

We were talking previously about EUV and the fact that it's been coming soon for a very long time, in the meantime 193nm lithography seems incredibly resilient. Did it surprise you how far you've been able to push 193nm litho ?

MB : If you had asked me ten years ago, "do I need EUV by 14nm", I would have said yes! So, even I have been surprised at the type of innovations our research has provided to extend immersion. So that's the good news.

A lot of these gains came from immersion in your perspective?

MB : Most of the gains from immersion itself were realized at the 32nm generation and then going forward from that we started to introduce double patterning and even triple patterning techniques. So that, combined with some other mask making improvements have enabled immersion to extend down to 22, and 14, and I know we have an immersion solution for the 10nm generation. Now, can immersion be extended to 7 ? We don't know yet. We're exploring that option; we are also pushing to advance EUV as quickly as we can.

You showed a pretty interesting graph [shown above] featuring the cost per transistor for various generations, and despite the fact that you may use multiple patterning on 14nm or other technologies that may push up some of the costs, you had a point pretty much in line with the other generations for 14nm ?

MB : At Intel we pay very close attention that each technology generation provides not only the expected performance and power gains but also the reduce cost per transistor. And as I've shown in my graph it's been pretty consistent for many generations. Is the wafer cost going up? Is the process complexity going up each generation? Yes. Are we able to find ways to improve density enough to offset that cost? The answer is also yes, at least down to the 14nm generation and I hope and expect a similar answer for 10.

During the press briefing this morning you were asked about the name change of what used to be the 16nm node, and that you are now referring to as 14nm node. Your answer to that was you managed to increase density. Could you elaborate a little bit more on that ?

MB : Only if you promise not to tell our competition ! But the name change is not just semantics. We took a close look at what our original density goals were for that generation, identified ways to do even better than normal in terms of scaling, and thus renamed it from 16 to 14.

In 2005, Intel's research group published a paper regarding the usage of III-V materials [materials from columns III and V of the periodic table of elements], at that time Indium and Antimony in order to build compound semiconductors [using two materials instead of one, silicon]. Can you talk a bit about further research on that topic?

MB : Yes ! Our research group has published a series of papers over the past four or five years on even better III-V channel transistors using I think Indium-Gallium-Arsenide [InGaAs] and Indium-Phosphide [InP], so, we're making steady progress on that front as a way to provide higher mobility transistors, and higher mobility can be translated to lower operating voltage, which means lower power. So that's one of several interesting transistor directions that our research group is exploring. Other transistors options include, instead of a finfet, a nanowire type structure for example that you can do with silicon or germanium.

Any comment on which one you see having the most short term potential? It would seem nanowire structures are a bit farther off than using III-V materials?

MB : I'm not going to comment on which is more or less likely. We're exploring a range of transistor options and exactly which one ends up being selected and best meets our needs is something we'll disclose later. But our research group, their job is to cast a wide net, explore many options and yeah, maybe some of them just don't work out, but a few of them do.

You mentioned Intel Research is working on MRAM, is there anything you can tell about that?

MB : Nope ! Other than that we are exploring different memory types (phase change, etc) in parallel of different types of transistors, and there may be interesting applications for those.

You were asked this morning about your thoughts on SOI [Mark Bohr's Answer was that SOI doesn't provide a cost effective solution]. A lot of your competition is talking about Fully Depleted SOI for the upcoming nodes, is your answer still the same regarding that ?

MB : When you talk about FD-SOI, you're talking about planar Fully Depleted SOI ? There's only one company that I know of that has strong interest in that, ST Microelectronics.

IBM also ? [we were referencing this article]

MB : Well, several companies are researching that, but are companies committing products to that ? The only company that I'm aware of that has expressed a strong interest in FD-SOI products is ST Microelectronics.

I think other companies; you know, haven't been very clear and certainly haven't committed to it. I haven't seen any strong commitment to that from GlobalFoundries, TSMC or Samsung. I think the major players are focusing more on FinFET/TriGate solutions as opposed to plannar Fully Depleted SOI. But again, FinFET and TriGate will be done and can be done on either bulk or SOI. Some people may choose to do that on SOI, and others on bulk.

Historically, I think you haven't been a fan of the foundry business model [eg TSMC and GlobalFoundries with multiple customers], yet Intel has a (very) small foundry business [with Achronix and Tabula]. Did this experience change your opinion a little bit, that the foundry business may have some merit to it?

MB : I think what we are saying is we know we have the industry's most advanced technology. We know that other companies would like access to it. So our primary interest is to be a foundry supplier to some strategic customers. A secondary benefit is maybe you learn a little bit in that interaction with them on how to better tune or optimize the technology for a broader range of products. But that's a very minor motivation. The primary motivation is we have the technology, we think it has value and we have some very interested customers.

As you said, considering the value of the process, and that the gap with your competition seems to widen, wouldn't it make sense to tighten up more and not open at all your process?

MB : Hmm. I think opening up our fabs to some selected, strategic customers makes a lot of sense from Intel's perspective. Becoming a general purpose foundry is not something that I think is right for Intel.

We'd like to thank Mark Bohr for sharing his time for this interview.

Autre articles dans le même thême
AMD A10-5800K and A8-5600K: the second desktop APU! AMD FX-8350 review: is AMD back? Intel Core i3-3110M Ivy Bridge versus i3-2370M Sandy Bridge Interview with AMD's CTO Mark Papermaster: SoC? x86?
AMD A10-5800K and A8-5600K: the second desktop APU! AMD FX-8350 review: is AMD back? Intel Core i3-3110M Ivy Bridge versus i3-2370M Sandy Bridge Interview with AMD's CTO Mark Papermaster: SoC? x86?

Copyright © 1997- Hardware.fr SARL. All rights reserved.
Read our privacy guidelines.