The Nehalem
A little surprise at this IDF was a Nehalem in action ! Although the processor is still in development, Intel showed that indeed it is well advanced and functional. Or at least partly so, because it is already capable of booting Windows while its release isn’t before the end of 2008.
The Nehalem introduces itself to Paul Otellini.While Intel hasn’t yet revealed the details on the core of this new technology, an overall view is starting to form. Thus, we can’t say to what extent efficiency will progress nor what will be the real
capacities of these new cores. At most we know that HyperThreading will be back and that each core can pilot two threads in parallel.
We do already know that it will involve architecture than is more modular than what is currently in use. First of all, in terms of the number of cores, Intel mentions 2, 4 and 8 core versions. However, for optional integration, there will be a graphic controller! The Nehalem in fact will have a memory controller, as AMD has done for some time now, and according to Intel it’s only logical that the memory and graphic controller are close. This is also a way to totally do away with the northbridge, of which only a PCI Express hub will remain.
It’s evident that Intel will not produce every variation possible and we can only wonder what physical form this processor will take. We do know that Intel will make a Nehalem die which will consist of 731 million transistors. It could possibly be the 4 core version which Intel revealed.
On the below photo of the die, we can indeed distinguish 4 cores, L2 cache on the bottom, and theoretically, the memory controller above. Intel has not yet unveiled the size of L2 cache, however, we can suppose that it will be 8 MB. The photo does not show an L2 and L3 cache structure as previous (vague) information from Intel lead us to believe.
They did, however, confirm that the memory controller would be a triple channel type, something which will better feed the processor given the slower evolution of memory compared to the number of cores. The FSB disappears and the Nehalem will rely on a new type of bus to communicate with the rest of the system. This bus, first of all called CSI for Common System Interconnect, has just been renamed QuickPath. This is similar to HyperTransport, but in principle, Intel should try and avoid going towards a technology developed by AMD.
Concerning modularity, there are a number of possibilities. Intel could produce other dies, which have 8 cores, for example, or 2 cores in order to offer very low priced processors. There could also be the placement of 2 dies with 4 cores in the same package like they currently do. Die stacking, the technique consisting of piling 2 dies on top of each other, has also been mentioned. In our opinion however, this solution seems a bit unrealistic for the release of the Nehalem given the numerous challenges in this area. This is all the more so considering the significant amount of heat produced by two chips.
As for the integrated graphic controller? In all Nehalems but only activated on some? Only integrated in 2 core versions? We will have to be patient to get these answers.
