Every 6 months, Intel summons the international press to the IDF, the large technology forum used by this manufacturer to inform and shape the industry on its upcoming technology. As has been the case for several years now, this Fall 2007 edition took place in San Francisco. Last February was the exception as it was held in China. In the future, Intel should alternate between Peking and San Francisco for the major IDFs with the gained importance of the Asian market.
Compared to the IDF in Peking, forget the traditional dance shows, priority for members of the Party, and police at every door, and hello again to an American style expo. This time, Intel took less effort to blend in with Chinese propaganda and they concentrated on the essentials. Of course, the location of this IDF wasn’t the only reason for a more direct Intel and timing was probably the most important component.
With the upcoming release of the Penryn and when the question of massively multi-core processors is becoming more and more relevant, it was only logical to expect something more concrete from Intel. And we got it!
Manufacturing technology
Each IDF is the occasion for Intel to show that it’s the king in this domain. This year did not deviate from this tradition and there was a presentation for the first time of a test wafer produced with the future 32 nanometer production process. This process is not as revolutionary as was the 45 nm, but it still allows doubling the density of transistors, and in other ways to conceive a chip twice as complex for the same size.
The first 32 nanometer wafer and the resulting chip.The first processor to use it will be the Westmere, a « light » revision on the architecture introduced by the Nehalem. If everything goes well, this will be followed 1 year later by the Sandy Bridge, a new architecture. For the time being, the wafer presented by Intel consists of a classic test structure, in other words, with SRAM memory, and all sorts de test circuits in order to debug and optimize the production process.
You might recall that Intel’s strategy consists of alternating between "Ticks" and "Tocks", by introducing new manufacturing processes during the Ticks and new architectures in the Tocks in order to reduce the associated risks.
