AMD K10 architecture (page 7: Various optimizations)

Prefetchers

The K10’s cache sub-system also gains from better hardware prefetchers than the K8. You may recall, the functioning of the prefetcher is based on the principle that a failure in reading has a strong probability of occurring, which will mean going back to instructions or data in the central memory.

The K10 has two hardware prefetchers which feed its L1 caches, while those of the K8 operate in the L2. The K10 additionally benefits from a new prefetch device in the memory controller which has a dedicated storage buffer.

Various optimizations

The K10 strives to correct several of its predecessor’s defects. The K8 “suffered” from rather slow integer division in comparison to rival Core architecture (particularly compared to the 45 nm version, which you may remember, benefited from an optimization specific to this type of operation). The K10 remedies this without entirely attaining the performance of the 45 nm version of the Core 2.

The adoption of “out-of-order” management in reading memory instructions is much more interesting. Present on the Core 2 and called “Memory Disambiguation” by Intel, this speculative mechanism’s aim is to predict if a reading instruction is susceptible to be dependent on writing in progress. Otherwise, the reading is processed without delay.

Also, note that there is better management of the stack (its management instructions are now handled by a dedicated unit), as well as several updates for the support of extended instructions, in particular certain SSE3 ones absent from the K8 and a new SIMD series of instructions grouped under the name, SSE4A (no relation to Intel’s SSE4.1 and SSE4.2, which would have been too easy).

Improved virtualization support

The K10 proposes a series of optimizations which aim to accelerate the processing of virtual machines, for example, improved memory management or the reduction of time in the transition between the hypervisor and virtual machines.