This week AMD announced the first model of its new microarchitecture, the "Barcelona" server version of the much awaited K10. We will still need to be patient for a few months in waiting for the arrival of general public and desktop versions, the Phenom X2 and X4, which won’t be available before December. Here is a glimpse of the architecture that succeeds the very popular Athlon 64.
Staying in the race
The arrival of Intel’s Core architecture in June 2006 made waves in the processor world and the new processor quickly stole the show from the Athlon 64 in terms of performance, thermal dissipation...and price. Intel struck hard forcing AMD to drastically revise its pricing structure (almost a 50% reduction for the Athlon 64 X2) in order to stay in the race if not technologically then at least commercially.
A mere few months after the introduction of the Core 2 Duo, Intel did it again by introducing the first quad core processor. This was another tough blow for AMD, who in addition to being late on the 65 nm process, didn’t offer a single commercially viable solution against the Core 2 Quad.
AMD bought some time by getting all it could out of the K8. A 65 nm version of the processor appeared in December 2006. The Brisbane core was intended to overcome AMD’s tardiness in terms of thermal dissipation and the Texan giant only came out with a 512 KB L2 cache version thus keeping it out of the high end market. Then last August the ultimate version of the Athlon 64 X2 was released, the 6400+ set at 3.2 GHz and based on the 90 nm Windsor core.
In March, AMD’s Executive Vice-president, Mario Rivas, confessed that he would have liked to have seen the release of a “two times two core” version of the Athlon 64, in order to serve those most eager and be present on the quad core processor market. Instead, AMD’s commercial strategy consisted of arriving on the market with a new architecture that was designed and originally conceived to start with four cores.
The K10 changed its status from simply taking the baton from the K8 to being AMD’s savior. The new architecture is supposed to bridge AMD’s tardiness in a number of areas (four cores, 128 bit units, advanced energy management...), and we can’t help objectively wondering if this isn’t too much weight for the shoulders of a new and emerging architecture. It’s a sizeable challenge and as the delays get longer, the pressure and uncertainties grow. Several AMD directors have left the company and rumors are circulating of a buyout by a large micro-electronics group.
Presentation of the K10
The characteristics of the K10 have been public for several months now.
- Four core architecture;
- A yet unseen cache hierarchy: 128 KB of L1 cache and 512 KB of L2 per core, unified L3 cache of 2 MB ;
- SSE 128 bit units ;
- DDR2 memory controller integrated to the processor;
- Advanced mechanism for energy management (Independent Dynamic Core Technology);
- 3 HyperTransport 1.0 lanes (Barcelona), one HyperTransport 3.0 lane (Phenom) ;
- 463 million transistors engraved in 65 nm SOI technology.
