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Intel Core 2 Duo - Test
by Franck Delattre et Marc Prieur
Published on July 4, 2006

The Netburst plan
  • 20 stages (Willamette and Northwood cores), for a maximum frequency of 3.4 GHz.
  • 31 stages (Prescott and Cedar Mill cores), for a maximum frequency expected of 5 GHz
  • 45 stages (Tejas core), to reach over 7 GHz.Of course there are some limitations to the increase of the number of stages of the pipelines. Beyond 55 stages, the IPC reduction due to the above mentioned factors is no longer compensated by increases in clock frequency and the number of instructions per second. In consequence, performances begin to decrease.

    (source Intel)

    Unfortunately, the first Pentium 4 Willamettes weren´t very efficient except maybe for the 2 GHz version. Indeed the theoretical model showed that performances were only there if clock frequency was high enough to compensate for the IPC reduction. The Willamette between 1.3 and 1.5 GHZ only partially fulfilled this condition, while the Northwood spectacularly rectified this situation. This was because on the one hand there were much higher frequencies and also much bigger and faster cache than the Willamette. The result was the increase of the success of the cache sub system and the reduction of penalties due to memory accesses. Northwood versions from 2.8 GHz really proved the worth of Netburst. The 3.2 and 3.4 GHz versions are still up to now models of performance and are very much sought after in the second hand market.

    In June 2004, Intel moved to the second phase of the Netburst plan and introduced the Prescott. Even if it included more cache memory than the Northwood, it surprised us in tests because of two points: performances were in some cases inferior to the Northwood and the new processor even if it has a 90 nm fabrication process tends to reach very high temperatures. The performance drop compared to the Northwood is explained by the pipeline depth increase to 31 stages. The excessive heat however was a very bad surprise and the Prescott never completely rid itself of this problem despite noticeable improvements in stepping. In the end, the thermal dissipation issues broke the progression of the Prescott and the situation turned somewhat sour. The Prescott was stuck in frequency increases, which led to doubts about the entire Netburst architecture.

    The problems of Netburst
    Northwood already suffered from significant thermal dissipation even if the problem was not as great for the Prescott. If thermal dissipation remained acceptable for a desktop or server platform, it was a real problem for the mobile, because of the heat and autonomy. Even if the Pentium 4 exists in a Mobile version, Netburst architecture has never really been adapted to low consumption use. A new architecture was required for this domain.

    Parallel to Netburst, there was a mobile architecture that was developed based on the P6 and whose first representative was the Pentium M Banias released in March 2003. Even if it was a success allying performances and energy saving features, Mobile gave a hard time to the Netburst. Intel had to produce two different architectures to cover all computer platforms. Of course, this meant higher production costs compared to a multi-use architecture and this was a first set back for Netburst.

    One reason there was high thermal dissipation was due to high frequencies. This wasn´t the only reason, however. At equivalent frequencies, the Prescott dissipates more energy than the Northwood despite a lower fabrication process. The difference in fact comes from pipeline depth. More stages increase power dissipation due to something called cut up.

    To understand, you have to know that some of the critical steps in instruction processing need to be made in one clock cycle. If not, this considerably slows down pipeline functioning. This is the case of branching production or the out-of-order engine that may lead to dependencies. These key stages aren´t really good candidates to the cut up and have to finish their work in one clock cycle.

    The longer the pipeline is, however, the smaller the clock cycle. In order to compensate for this decrease, it’s necessary to parallel algorithms used by these stages in order to finish their work in the time allowed. This parallelisation considerably makes the stage more complex and the number of transistors that it requires, amongst others things. Also, if the only algorithm change is not enough to finish the operation in one cycle, it’s necessary to use faster, bigger and more power hungry transistors. This of course leads to an increase in thermal dissipation and is all the more critical because of the intended low clock cycle and pipeline depth.

    The following example particularly illustrates this constraint. The Northwood has “double speed” whole number calculation units that make it possible in practice to complete two operations per clock cycle. The Prescott’s pipeline length increase didn´t make it possible for the integration of such ALUs. In order to keep the same instruction transfer rate, each double speed ALU has been turned into two single speed ALUs. This of course doubled the number of transistors used by the units in question.

    The Prescott turned each double speed ALU of the Northwood into two simple speed ALUs.

    We ask ourselves where Netburst would be today if there weren´t the heat dissipation issues, if the cryogenic cooling system would replace Intel´s standard CPU fan. The Prescott would run at 4.8 GHZ and the Cedar Mill version would be at over 5 GHz. The Tejas would be about to be released with the SSE4 instruction set (initially called TNI for « Tejas New Instructions ») and a 45 stage pipeline.

    The objective of this projection isn´t to show you how idyllic the Netburst architecture is, but rather to make you understand that the abandonement of Netburst wasn´t motivated by performance issues. In the end, the final thermal dissipation didn´t make it possible to reach the frequencies required at the targeted performance.

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