New processor, new core
The Athlon 64 Socket 754/939 has already undergone several core changes during the past few years. The SledgeHammer and ClawHammer (1 MB of cache L2) and the Newcastle (512 KB of cache L2) had 130 nm fabrication processes. The 90-nm release came progressively via the Winchester core. With 512 KB of cache L2, it doesn’t reach over 2.2 GHz for a sales product, the Athlon 64 3500+ Socket 939.
For the past few months now, Athlon 64 processors are based on a new core. This "E" revision core is available for Athlon 64 processors in a version with 512 KB cache L2, the Venice, and a 1024-KB cache L2 version, the San Diego. Unlike the Winchester, the Venice et San Diego cores aren’t restricted only to the most entry-level products but are available for the whole processors’ range. The San Diego isn’t restricted to the new FX-57 but it is also used for the other A64 1 MB, the FX-55, 4000+ and 3000+.
There are several improvements with this new core. The first one is the manufacture and the Dual Stress Liner use. This technique developed by AMD and IBM is of a "strained silicon" type. It allows the electrons’ moving speed to increase in the transistor, so as to facilitate the frequency increase and/or reduce the power consumption.
The memory controller has also been improved. Yesterday, it supported a maximum of 4 single-side memory modules (8 chips) in DDR400 2T, and 4 dual-side (16 chips) memory modules in DDR333 2T. It is now possible to be respectively in DDR400 1T and DDR400 2T mode with this type of memory module. We remind you that 2T or 1T means a latency of 2 clock cycles or 1 clock cycle for the Command Rate. This is the latency between the RAM selection and the transmission of a command to this one. It isn’t the only improvement as AMD has also improved the data pre-loading, in addition to the write-combining buffers’ number.
The first add-on is the Intel SSE3 instruction set. SSE3 instructions aren’t a new full instruction set, but more like a complement to current instruction sets:
- 1 x87 instructions (FPU) for the floating number conversion to whole numbers (fisttp)
- 3 SIMD 128 bits instructions for data duplication (movsldup, movshdup, movddup)
- 1 SIMD 128 bits instruction for non-aligned data load (lddqu)
- 2 SIMD 128 bits instructions for addition in vertical calculation (addsubps, addsubpd)
- 4 SIMD 128 bits instructions for addition/subtraction is horizontal calculation (haddps, hsubps, haddpd, hsubpd)
Two other SSE3 instructions for thread, monitor and mwait synchronization were not included by AMD in the Athlon 64 and to the Athlon 64 X2 based on the "E" core.
In the end, it leads to a higher number of transistors: for 1 MB of cache, the number of transistors increases from 105 to 114 million and for 512 KB of cache from 68.5 to 76 millions. Because of the lower manufacturing process, the dies are however less big: the size is reduced from 193 to 115mm² and from 144 to 84mm². Of course, this leads to reduced production costs for equivalent yields because it is possible to make more processors out of the same silicon wafer.
