Corsair XMS 3200 XL
by Marc Prieur
Published on June 14, 2004
For almost a year now, the original DDR1 has little or none evolved. The manufacturers focus logically their research effort on the DDR2.
Lately, no chips released disturbed the results of our last 16 PC3200 memory (and above) and four 1 GB PC400 set comparative test. And even if a few manufacturers created the PC4400 after an upgrade of the Hynix and of the memory selection.
The only problem is the shortage of Winbond BH5 chips. No chips took over the BH5 despite a promising CH5 version. Winbond actually decided to leave the standard memory market.
Corsair is now coming back on the market with the impressive XMS 3200 XL memory:
Frequencies and timingThe two main parameters for the memory are: on one side the frequency and the timing on the other side. The current frequencies on the market are:
- 133 MHz : DDR266/PC2100
- 166 MHz : DDR333/PC2700
- 200 MHz : DDR400/PC3200
- 217 MHz : DDR433/PC3500
- 233 MHz : DDR466/PC3700
- 250 MHz : DDR500/PC4000
- 275 MHz : DDR550/PC4400
Only the three first frequencies have specifications officially acknowledge by the JEDEC. The frequency memory is a part of the whole system. And indeed regarding the quality of the memory chip used, some of them are quicker than other to process the requested operations. The four main characteristics are (of course amongst others) are the tCAC, the tRCD, the tRP and the tRAS:
tCAC: (column access time) it is the minimum amount of time required to access a column from a memory bank
tRCD: (RAS\ to CAS\ delay) it is the minimum amount of time to access a line from a column.
tRP: (RAS precharge time) it is the minimum amount of time between two RAS signals (activation of a memory bank).
tRAS: (active-to-precharge delay) it is the minimum amount of time required to access a line from a memory bank.
These data are expressed in nanoseconds (ns). We use another value to calculate the latency time, expressed in cycles, which will be configured on the RAM module, or eventually used in the BIOS.
tCLK: (the clock speed) time for one cycle. It is calculated by 1/ bus frequency, and is of 10 ns at 100 MHz, 7.5ns at 133 MHz, 6ns at 166 MHz and 5ns at 200 MHz.
We use then the next formulas to find the following latency time (expressed in cycles):
CAS Latency: tCAC / tCLK
RAS to CAS Delay: tRCD / tCLK
RAS Precharge Time: tRP / tCLK
RAS Active Time: tRAS / tCLK
Generally results are given in this order: 2-2-2-6 or 2-5-3-3-8
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