R&D : CMOS

At this IDF, Intel put much effort into reassuring us of the future of its technology. There have been doubts on limitations of CMOS technology for the middle term for transistor performance and manufacturing, but Intel clearly said that it looks positive in this area and their R&D department is mainly working on three technologies.

Evolution of the manufacturing process

It´s the easiest way to continue transistor evolution. Changing the process permits a higher number of more efficient (higher frequency) and smaller transistors (it´s possible to place more transistors on a single CPU for the same cost). Intel’s success is partly due to the manufacturing process and a large number of factories, allowing massive processor production with excellent yields.


At the end of this year or early 2006, Intel will release the first 65 nm processors. The process will be based on the same technology as the current 90 nm. It will use Strained Silicon, which increases the electron speed in transistors, facilitates the increase in frequency and/or reduces power consumption. In 65 nm Strained Silicon will reach the second generation and, according to Intel, transistor performances will be increased by 30%.

While defending its technology, Intel doesn’t hesitate to attack that of its competitors, SOI, which allows reduction of leakage (which only increases CPU temperature) and, therefore, power consumption. AMD, however, appears to be very satisfied with this solution, and the Athlon 64´s low thermal dissipation strengthens this position. According to Intel, SOI as used by AMD (partially depleted) has no interest whatsoever, because it only reduces one type of leakage, significantly increases production costs and doesn´t serve the evolutionary process. Intel will only consider the SOI in its « fully depleted » version, which means with an extra thin layer. This wouldn´t be for now, however, and the decision will be based on a cost /gain ratio for this solution in a couple of years.


In 2007 with the 45 nm process, an important modification will take place with the use of high-k type dielectrics to insulate interconnections between transistors and metal electrodes (instead of the current use of silicon oxide and poly-silicon). This important modification will reduce the grid capacitance (increasing transistor speed) and reduce leakage by a factor of over 100. Power consumption will consequently also be drastically reduced. All these modifications will make it possible to produce a quad core CPU with a high frequency and power consumption below 100 Watts.

Die Stacking

This isn’t really a new technology as it´s been used for memory for quite some time now. Die Stacking consist of piling dies, one on top of another and connecting them to each other or directly to the socket. There are of course physical limitations in establishing these connections and also for heat dissipation. Piling up four Prescotts could be indeed quite dangerous.

Piling cores with lower heat dissipations is possible, but for the now, there is talk of completely different dies. For example there would be a CPU, one Northbridge, one network controller and very fast RAM piled up. The space gain would be consequent and costs reduced. If it is difficult today to imagine this type of configuration with current CPUs, the situation is different with the Pentium M LV and ULV. With these processors this technology will entirely take form.


There is still of course the need to develop an efficient and reliable packaging system (to avoid crushing the die when installing the cooling system, for example), the available inputs and to solve the thermal dissipation issue. For this last point, Intel says that several solutions exist and that it won’t jeopardize the process of Die Stacking.

Photonic CPU

One growing problem in CPUS is the delay of signal propagation in interconnections. A couple of generations ago it was considered negligible, but today this is no longer the case. Transistor transmission speed has been seriously increased whereas propagation time has remained more or less steady. This situation is logical, because with miniaturization even if the distance is smaller the signal uses thinner interconnections with a higher resistance reducing the signal speed. With one thing and the other propagation time has remained steady.


This die distributed by par Intel includes no less that 8 lasers
If a signal needs to move from one CPU block to another, it can no longer do it in one cycle. A repeater will need to be included, which increases power consumption and signal latency. Solutions are available with the improvement of the fabrication process, but this may not be enough for the long term.


One solution could be the use of photonic on silicon, which is the same thing as using photons (light) instead of electrons to transmit signals. Gains are very significant, because the signal is faster and much less damaged. We could imagine in years to come a photonic connection to the cache L2 or even external photonic connections to the CPU to connect two dies and various other uses in many areas.


This could prove challenging, however, as ideally photonic elements will have to be made of the same materials as the transistors. Unfortunately, the photonic needs a light source, a laser. The laser needs to work with a material, which easily and massively emits photons. This is absolutely not the case with silicon.


Is there a solution? There is for Intel, which has announced the development of the first continuous laser with silicon. Based on the Raman effect, this quantum effect allows the magnification of optic signals. A pump makes an electron flow and the Raman amplifier efficiently magnifies the signal. The Raman effect is 10,000 times stronger in silicon than in optic fibers. Does it work? Not yet, another problem exists and makes the laser unusable. In normal use, the silicon is transparent to infra red light, but during amplification the photon number increases so much that two simultaneously hit a silicon atom with some regularity. The result of this collision is an electron, which absorbs a great number of photons and reduces the Raman effect to zero. Intel said, however, that this is only a first step and that other problems will be solved in years to come.

The CMOS lives

With future CMOS fabrication processes, Die Stacking and the silicon photonic, Intel still has its work cut out for it. There is enough here to continue to create more evolved and efficient CPUs for at least the next two decades!

Intel didn’t hesitate to give a quick preview of the CPU in 2015. It will be strongly optimized for multi-threading, integrate several cores and in addition will have more specialized units like what IBM will start to develop next year with the Cell.

Intel 3.0

Intel 3.0

Not so long ago, Intel’s product development was split into two main divisions. The Architecture group dealt with standard processors and chipsets, and then there was the Communication Group for flash memory, processors for handheld peripherals, (PDA, GSM…) and network products. Today Intel’s product divisions have been split into five parts: the Mobility Group (laptop platform and handheld), Digital Enterprise Group (professional platforms), Digital Home Group (general public platform), Digital Health Group (for health, medical research etc.) and the Channel Products Group (deals with product localization and Intel’s product adaptation to specific markets).

Some analysts qualify this reorganization as a Intel 3.0 version. Intel was initially a memory manufacturer, then delved into processors and now is a platform manufacturer. Each division is relatively independent in terms of technology and marketing, which could lead to contradictions. Intel’s marketing strategy could also become more aggressive and specific to cover the market and technological aspects, which were put on the backburners. These changes could be very beneficial for the final user with products closer to their requirements and may better fit the evolution of needs. 2005 and 2006 will be the years to evaluate the efficiency of this new organization.

Besides this reorganization, Intel’s CEO will also be replaced. Craig Barrett has decided to give the chair to Paul Otellini, who will in May become Intel’s 5th CEO after Robert Noyce, Gordon Moore, Andy Grove and Craig Barrett. Unlike the previous CEOs which all had brilliant engineering pasts, Paul Otellini, the current president and COO, comes from sales and marketing. Major changes in perspective? Not at all, according to the new CEO, who insists on the fact that next to the changes there will remain 20 years of Intel history. This change in CEO leads, of course, to other modifications. Above, Craig Barrett will replace Andy Grove for the Chairman position . Nothing else has been said for positions below. Who is going to take the President and COO position? The charismatic Pat Gelsinger? The reorganization has eliminated the Chief Technology Officer position formally held by him, and he is now General Manager of the Digital Enterprise Group. With this position his field of action has been reduced.

You may have understood the broader context. Intel is currently changing at a crucial technological turn, which is the abandonment of processor speed for the possibilities of platforms. This 180° turn is difficult to make, but Intel has intended to succeed starting from today.

Technologies

VT

VT or Virtualization Technology (code name Vanderpool/Silvervale) will permit the democratization of a hardware virtualization system, or in other words the use of several OSs with a single computer. Some software like VMware currently gives us this possibility but with some restraints and are only destined for professionals. VT will simplify the whole process. One possible use for the general public could be an OS devoted to computer security. If the OS is infected by a virus (a hardy strain, which prevents the antivirus to initiate and/or update), the OS “keeper” will be able to clean this virus and temporary disconnect the computer from the network to avoid the virus spreading. Unfortunately we can count on virus and other spyware developers to develop specific virus versions for VT or at least try. To be completely functional, VT will require a support from the OS, some of the drivers and graphic cards. Once everything is set up, it could be a major turn in computer architecture.

IAMT

The IAMT mainly targets professionals who manage servers or computer networks. The objective is to facilitate their tasks, giving them more power from a distance and, of course, reduce management costs.

I/OAT

I/OAT is an innovation, which was unveiled for the first time at this IDF. With improvements in network transfer rates, the CPU load to manage it became substantial. Intel has decided to adapt the platform in order to optimize the processing of data in the network.

LT

LT or LaGrande Technology´s aim is to help the OS improve computer security, like with the Palladium and Longhorn. Unfortunately, we don’t know have much information in this area, and the Microsoft Palladium technology´s possible misuses have already been the subject of many articles. Everyone would like to see improved security, but nobody wants to see the major music corporations in their computers. LT / Palladium could invade our computers during 2006 and have implications on the CPU and chipset, graphic card level etc. Protected content could be encoded in all computer components. Potential abuse is also many fold and very lucrative businesses will appear.

EM64T

And of course the EM64T, Intel’s answer to AMD’s x86-64 was touted by the manufacturer even if it put its importance in perspective. The EM64T essentially permits better code optimization and to address more than 4 GB of memory. Of course, the chipset is also part of the memory support. The future i945 and i955X will be restricted to 8 GB. Microsoft was also present to remind developers that they will have to use the 64 bits as soon as possible. Windows Server 2003 64 bits will be available within a month and Windows XP 64 bits in a couple of months. The only negative for 64 bits was Intel skipping this technology for mobile CPUs.

Desktop

Desktop

Anchor Creek will be the high end 2005 platform. In 2006 it will be mainstream for the home market whereas Lyndon will be the office version. These platforms will support the Smithfield and Presler Pentium Dual-Core and also the single core equivalent (Pentium 4 and Cedarmill). It is only from mid-2006 that the Averill platform will be available along with several technological innovations: VT, IAMT, I/OAT and LT.

The i955X chipset of the Anchor Creek platform will bring a few innovations such as DDR2-667 support and 2 PCI Express “graphic” slots similar to NVIDIA’s SLI solution. But will it be possible to run the SLI with an Intel motherboard? Probably not, unless NVIDIA changes the driver policy.

Dual-core desktop

Expected for a long time, the Pentium 5 finally won’t be released. Intel has decided to leave the number and only keep the Pentium name, a strategic choice, which separates the product name from the technology. Desktop dual core processors will be named Pentium eXtreme Editions for very high-end models and Pentium D initially for the high end market and then for the mainstream market. All processors should be available before summer.


The processor which is code named Smithfield is made of a single block based on the current 90 nm process, but “only” uses the 1 MB version of the Prescott core. It integrates optimizations related to Prescott 2 MB power consumption. Despite this the processor´s thermal envelope remains enormous, because of the 130 W and it´s clocked at 3.2 GHz. Actually, Intel had to review the cooling system to take this thermal dissipation into account. The new one still has a rather standard size and doesn’t seems excessively noisy.

In 2006 the Pentium D will evolve and use a different solution, multi-die. This consists of placing two die on a single socket instead of integrating one die directly to both cores. Intel said it made the multi-core choice or multi-die per period and according to estimated fabrication process yields. The Presler will be made of 2 distinct Cedarmill dies. The Cedarmill also available in a single core version will be based on the 64 nm fabrication process, will feature 2 MB of cache and several optimizations, which weren’t specified by Intel.

Mobile

Mobile

Intel changed the roadmap for the mobile platform. The delay in the Sonoma announced at the end of January has repercussions on the Napa, whose release date has been postponed from the end of 2005 to early 2006. The new chipset, in addition to Dual-Core compatibility will integrate a new graphic core and a new smaller Golan WiFi component, whose power consumption will be lower than the relatively consumptive current component.


Golan will be a more compact WiFi component with a lower power consumption

Mobile dual-core

Expected at the end of 2005, the Yonah will be the first dual- CPU for laptops. Like the Smithfield, the Yonah will use a single die including both cores. This, however, is the only similarity. The Yonah will be necessarily based on the new 65 nm fabrication process, because there can´t be an excessive heat source in a laptop. Mooly Eden, the Mobility Group Vice-President said that the Yonah´s average power consumption will be equivalent to the current latest Pentium M. This, despite the presence of two cores and thanks to more advanced energy saving systems and, especially with the possibility to deactivate one of the cores.


One Yonah particularity is that it is the only Dual-Core CPU in Intel’s roadmap to use a shared cache L2 instead of two distinct caches. It will be 2 MB and provide equivalent performances to the Dothan cache L2. It´s also the only CPU of Intel’s roadmap not to support the EMT64! The 64 bit mobile will not be available until the end of 2006 for Intel. This situation could be a great opportunity for AMD and the Turion even if the 64 bit improvement hasn’t yet been proven.

The Yonah will include several innovations on the architectural level. Intel´s objective is to improve FPU and SSE performances in order to standardize them with the whole line of CPUs. Current ones are indeed a little behind in this respect compared to the Pentium 4. To successfully increase performance Intel has decided to increase the decoder transfer rate for SSE instructions. All 3 decoders now have the capacity to process SSE instructions. Some SSE operations will then be fused by the Micro Ops Fusion Engine like some instructions of the current Pentium M. And finally, SSE3 will be supported and the FPU slightly modified to improve performance… for games! Does the fact that Mooly Eden modifies the Pentium M use for games mean that the Yonah will be of interest for other products than laptops?

Server/Workstation

Serveur/Workstation

The Itanium platform will keep the same ageing chipset for 2005 and 2006. Intel has abandoned the Bayshore development project, a new chipset compatible with the latest technologies such as PCI Express.


To the Xeon platform we added a platform with a Pentium D, which will use the Mukilteo, a server/workstation uni-processor chipset. It is an interesting economical alternative to the bi-processor solution of 2005. We will have to wait until 2006 to see the release of the Xeon Dual-Core and a platform, which will bring several innovations; VT, IAMT and I/OAT.

In the years to come, Intel’s server platforms will include a new memory interface, which will use FB-DIMM (fully-buffered DIMMM). The FB-DIMM places an intermediate step between memory chips and the controller.
It allows the use of standard memory chips with a much different memory controller, the intermediate step processing some sort of conversion. With the FB-DIMM, the connection between the intermediate and controller will be of serial type, similar to PCI Express. It will provide higher transfer rates and will especially permit the use of more memory modules with a single machine.

Dual-core server

The famous Montecito, Itanium dual-core, which includes more than 1.7 billion transistor will be released at the end of 2005. It will be used with servers equipped with 4 or more processors, whereas the Milington will be the version used with bi-processor systems. It will feature several new technologies such as Pellston, which improves cache reliability, and Foxton technology, which allows automatic 10% Overclocking.


In 2006, these CPUs will be replaced by the Montvale, which is clocked higher. All of these CPUs will have a 90 nm fabrication process. We will have to wait for the Dinoma (DP) / Tukwila (MP) process in 2007 for the 65 nm. These Itaniums will mark the fusion between the Xeon and Itanium platform, which will use the same electrical interface and socket and have an identical price. In the beginning, the Tukwila sought to integrate a minimum of 4 cores, but Intel decided to change their plans reducing it to 2 more efficient ones. Still in 2007, the Poulson will take over the Tukwila (with more integrated cores?). You will notice that Intel, even if it doesn’t provide further details, clearly indicates that numerous Itaniums are currently in development and reaffirms its confidence in IA-64 architecture.


The first Xeon dual-core will be the Dempsey, equivalent to the Presler, which will actually be released in 2006. Intel also seems to have the ambition of reaching 65 nm with a smaller thermal envelope in order to attack the server market with dual core processors. The Dempsey, however, will be restricted to a dual core, and the Multi (quad) Processor will use the Paxville core based on the Smithfield. Intel’s MP CPU versions are generally one generation late for the fabrication process, which facilitates development. Nevertheless, we are already imagining the cooling solution required for a system with 4 Paxville. In 2007 at the time of the Xeon and Itanium platform fusion, Intel will release the Whitefield, a completely different CPU from other Xeons, because it will be made of 4 Pentium M cores!

In your living room, Conclusion

Intel in your living room

Like many in the IT industry, Intel wants to make it into your living room. This market will quickly change in the years to come, and it´s important for an actor like Intel to take the best position from the start.

The first system to invade our homes will be the next generation in consoles. Unfortunately for Intel, none use their CPU. All console manufacturers are buying IBM’s processors and Intel will have to fight to get a share of this market.


Intel has also presented several living room computers, which almost re-invent the recently released Apple Mac Mini. For the first time, Intel showed one of theses computers with a platform based on the Pentium M. It´s an important change as the Pentium M has never been officially considered outside of the mobile market. The Yonah will fit perfectly here with improved media processing capacities, the dual core and lower power consumption, permitting compact formats and low noise levels.

Intel won’t only conquer our living room, but also our cars. A technician from MTV´s show, Pimp my Ride, came to present their latest creation to Craig Barrett. It was an unrecognizable car equipped with a Centrino and most of the controls can be made at distance from a PDA.

Conclusion

This last IDF was an occasion for Intel to strengthen its engagement to multi cores instead of the frequency race. This important change took place a few months ago and is about to be finalized. The road, however, is still full of obstacles as only a few general public products are really able to benefit from the dual core. Of course, even if the resulting performance gain is not for today the comfort of use is! The system is more reactive, more efficient for multi tasks, and will provide better performance for specific applications. This is already a good start and sufficient to justify the quick introduction of the dual core even if it will only initially interest a small part of the market.


Intel, which was behind in 2004 compared to AMD in terms of CPU efficiency and performance, intends to re-conquer the advanced user market and also place more CPUs in each home with platforms better adapted to the market. Intel’s reorganization and replacement of its CEO also leans toward an optimization addressing the market as you may have understood in this article. They also seem to have the intention of maintaining the R&D tradition, which leads us to believe that the future will be rich in technological innovations.

If we like all these changes, we still have to keep in mind that we are still waiting for the implementation in practice of several technologies like EFI (a bios substitute expected for quite some time now), VT or even LT already presented by Intel during the last IDF. When will these technologies be implemented? Will LT bring significant restraints to the final user? What will be the exact specifications of future chipsets? We will have to wait a couple months more to have these answers. BR>